With the advent of multimedia communications, there arises the need for low cost solid state image sensors to complement computers and communication devices to realize practical videotelephones and the like. The image input device is central to any teleconferencing and multimedia application. Recently, CMOS image sensors have been recognized as a viable candidate for the image input device. CMOS image sensors also have utility in other fields such as robotics, machine vision and automotive applications. An important advantage of CMOS image sensors (or imagers) is that signal processing circuits can be readily integrated on the same chip as the imager, thus enabling the design of smart, single-chip camera systems. CMOS imagers are inherently lower cost than conventional charge coupled devices (CCDs) because they can be manufactured in conventional, widespread CMOS fabrication lines without any process modification.
FIG. 1 schematically illustrates one example of prior art active-pixel CMOS imager circuitry. Imager 10 is single-stage image sensor as disclosed in an article by Mendis et al., entitled "A 128.times.128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems", IEEE Electron Devices Meeting, p. 583, 1993. A MOS photogate 6 is employed as the light sensitive element in each pixel (imager cell) 18. The transistors within each pixel 18 are typically NMOSFETS. The overall imager 10 is considered a CMOS imager since CMOS electronics are used in conjunction with the imager cells. For example, the transistors 3 within readout circuit 31 are typically PMOSFETS. As shown in the simplified block diagram of FIG. 2, imager 10 includes a plurality of such cells 18 arranged in an array of rows R.sub.1 -R.sub.M and columns C.sub.1 -C.sub.N. Typically, only one row at a time is activated for image charge readout from all the cells 18 in that row. Timing and control logic 14 provides row select signals (VROW) on row select lines RSL.sub.1 -RSL.sub.M to select the active row. RESET pulses on lines RES.sub.1 to RES.sub.M are also generated by logic block 14 for application to cells 18. The light-induced charge from each activated cell is read out as a corresponding voltage on one of column buses 15.sub.1 to 15.sub.N, each of which is connected to the cells 18 in respective columns C.sub.1 to C.sub.N. The voltage on each line 15.sub.i corresponds, at any given time, to the image charge of only one activated cell in the associated column C.sub.i and activated row. Readout circuits 31.sub.1 to 31.sub.N read out the voltage of the activated cell in the corresponding column C.sub.1 -C.sub.N. A load transistor 28 is utilized on each column bus. Capacitance Cc represents the bus line capacitance. Bus lines 19.sub.1 to 19.sub.M carry voltages VDD, V.sub.PG and V.sub.TX to the respective cells 18. Processing/image storage electronics 16 receives the voltages from the readout circuits for storage in memory and subsequent processing and display. Logic blocks 14 and 16, which are clock synchronized, include CMOS electronics.
As shown in FIG. 1, within each cell 18 photo-charge "q" collected under photogate transistor 6 is transferred through a dc-biased transfer gate transistor 8 to a floating diffusion diode 7 formed beneath substrate surface 9. This floating diode 7 is periodically dc-restored by the application of a logic high RESET pulse to the gate of reset FET 11, thus resetting the potential of diode 7 (i.e., at circuit node 17) to a voltage determined by the threshold voltage of FET 11 and the power supply voltage (VDD). Following each diode reset cycle, the photo-charge is transferred to floating diode 7. The voltage on diode 7 then corresponds to the intensity of light incident upon the associated imager cell 18. This voltage sets the potential of the gate of source follower FET 13, which amplifies or buffers the voltage appearing at its gate terminal for subsequent readout. When row select transistor 12 is turned ON by a VROW pulse on row select line RSL, the voltage at circuit node 17 is detected by readout circuit 31 detecting corresponding voltage on column bus 15.
The reset noise is removed by a variation of the correlated double sampling (CDS) technique as disclosed in an article by White et al., entitled "Characterization of Surface Channel CCD Image Arrays at Low Light Levels", IEEE Journal of Solid State Circuits, vol. SC-9, p.1, 1974. When used in CMOS image sensors, this correlated double sampling technique effectively removes the fixed pattern of noise of the image sensor arising from offset errors due to transistor mismatches in manufacturing. To remove reset noise of reset switch 11, the reset level measured on column bus 15 is subtracted from the signal level on the column bus, where the reset level is obtained just prior to the transfer of photo-charge to diode 7. As such, any offset errors due to transistor mismatches is canceled since both levels are measured at the same circuit point. In the embodiment of Mendis et al., the reset level and the signal level are stored on two separate sample and hold capacitors CR and CS, via two separate switches S1 and S2, respectively. Two identical readout circuit portions are required, one for the reset level, and one for the signal level. Further differential amplification at the multiplexed column output (within circuit block 16) is required to complete the reset noise removal operation.
One drawback of the Mendis-type imager 10 of FIGS. 1 and 2 is that the CDS operation is performed in the analog domain, using capacitors CR and CS to temporarily store the reset and signal samples, respectively. These analog circuits are susceptible to noise and gain errors, reducing the accuracy of the image data. In addition, the capacitor CR used to store the reset sample must have a large area to minimize noise. Accordingly, there is a need to overcome these deficiencies.